@dc42 The spreadcycle optimization documentation recommends enabling random off time (M569 P0 D1) or chopSync (not supported?), should I do that? Is stealthChop an option too? This is on Duet 2 Wifi.
It looks like there are several parameters that affect idle noise: TOFF, HSTRT, HEND, HDEC, RNDTF, CHM, TBL. I made a macro that goes through all possible permutations. Something like:
G91 ; relative positioning
M906 I100 ; disable idle-current reduction
M117 P"F1 Y0:0:0" ; Print message
M569 P2 F1 Y0:0:0 ; Set register
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
M117 P"F1 Y0:0:0 END" ; Print message
M117 P"F1 Y0:0:1" ; Print message
M569 P2 F1 Y0:0:1 ; Set register
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
M117 P"F1 Y0:0:1 END" ; Print message
M117 P"F1 Y0:0:2" ; Print message
M569 P2 F1 Y0:0:2 ; Set register
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
M117 P"F1 Y0:0:2 END" ; Print message
M117 P"F1 Y0:0:3" ; Print message
M569 P2 F1 Y0:0:3 ; Set register
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
G1 S2 Z-0.1 ; Move Z a little bit
G4 P1000 ; Wait 1000ms
M117 P"F1 Y0:0:3 END" ; Print message
and so on...
First I will find the best TOFF, then the best HSTRT/HEND/HDEC value, then the best RNDTF/CHM/TBL. Moving on to the next stage if the previous doesn't work.
It would look like this: M569 P0 F12 Y3:3:0 D1 B2 ; X, TOFF 12, HSTRT 3, HEND 3, HDEC 16, CHM rndtf, TBL 36 in the worst case scenario.
This is assuming that the following stage is dependent on the previous stage (i.e. HSTRT/HEND/HDEC is dependent on TOFF and I don't have to find TOFF again). Does this make sense?