OK, so far so good! It's been stable for a while now so maybe I can trust it I don't totally trust it. I had to change in a few more places.
@dc42 Well, that look promising 🙂
So now (I really hope it lasts):
Driver 0: pos 80000, 80.0 steps/mm,standstill, SG min 16, read errors 0, write errors 0, ifcnt 70, reads 13761, writes 1, timeouts 0, DMA errors 0, CC errors 0, steps req 0 done 0
Driver 1: pos 574280, 574.3 steps/mm,standstill, SG min 16, read errors 0, write errors 0, ifcnt 68, reads 13762, writes 1, timeouts 0, DMA errors 0, CC errors 0, steps req 0 done 0
$ git diff src/Movement/StepperDrivers/TMC22xx.cpp
diff --git a/src/Movement/StepperDrivers/TMC22xx.cpp b/src/Movement/StepperDrivers/TMC22xx.cpp
index 4b8a1acb..b301af8e 100644
--- a/src/Movement/StepperDrivers/TMC22xx.cpp
+++ b/src/Movement/StepperDrivers/TMC22xx.cpp
@@ -1441,7 +1441,7 @@ void TmcDriverState::AbortTransfer() noexcept
#if TMC22xx_USES_SERCOM
DmacManager::DisableChannel(DmacChanTmcTx);
DmacManager::DisableChannel(DmacChanTmcRx);
- sercom->USART.CTRLB.reg &= ~(SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN);
+ sercom->USART.CTRLB.reg &= ~(SERCOM_USART_CTRLB_RXEN/* | SERCOM_USART_CTRLB_TXEN*/); //UER
while (sercom->USART.SYNCBUSY.bit.CTRLB) { }
#else
uart->UART_IDR = UART_IDR_ENDRX; // disable end-of-receive interrupt
@@ -1497,17 +1497,18 @@ inline void TmcDriverState::StartTransfer() noexcept
regnumBeingUpdated = regNum;
#if TMC22xx_USES_SERCOM
- sercom->USART.CTRLB.reg &= ~(SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN); // disable transmitter and receiver, reset receiver
+ sercom->USART.CTRLB.reg &= ~(SERCOM_USART_CTRLB_RXEN /*| SERCOM_USART_CTRLB_TXEN*/); // disable /*transmitter <--- UER*/ and receiver, reset receiver
while (sercom->USART.SYNCBUSY.bit.CTRLB) { }
#else
uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX; // reset transmitter and receiver
#endif
const uint8_t regNumber = (regNum < WriteSpecial) ? WriteRegNumbers[regNum] : specialWriteRegisterNumber;
- SetupDMASend(regNumber, writeRegisters[regNum]); // set up the DMAC
+ //SetupDMASend(regNumber, writeRegisters[regNum]); // set up the DMAC <---UER
#if TMC22xx_USES_SERCOM
dmaFinishedReason = DmaCallbackReason::none;
DmacManager::EnableCompletedInterrupt(DmacChanTmcRx);
- sercom->USART.CTRLB.reg |= (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN); // enable transmitter and receiver
+ sercom->USART.CTRLB.reg |= (SERCOM_USART_CTRLB_RXEN /*| SERCOM_USART_CTRLB_TXEN*/); // enable transmitter and receiver <--- UER
+ SetupDMASend(regNumber, writeRegisters[regNum]);
#else
uart->UART_IER = UART_IER_ENDRX; // enable end-of-transfer interrupt
uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; // enable transmitter and receiver
@@ -1520,19 +1521,20 @@ inline void TmcDriverState::StartTransfer() noexcept
AtomicCriticalSectionLocker lock;
#if TMC22xx_USES_SERCOM
- sercom->USART.CTRLB.reg &= ~(SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN); // disable transmitter and receiver, reset receiver
+ sercom->USART.CTRLB.reg &= ~(SERCOM_USART_CTRLB_RXEN/* | SERCOM_USART_CTRLB_TXEN*/); // disable transmitter and receiver, reset receiver
while (sercom->USART.SYNCBUSY.bit.CTRLB) { }
#else
uart->UART_CR = UART_CR_RSTRX | UART_CR_RSTTX; // reset transmitter and receiver
#endif
const uint8_t readRegNumber = (registerToRead < NumReadRegisters) ? ReadRegNumbers[registerToRead] : specialReadRegisterNumber;
- SetupDMARead(readRegNumber); // set up the DMAC
+ //SetupDMARead(readRegNumber); // set up the DMAC
#if TMC22xx_USES_SERCOM
dmaFinishedReason = DmaCallbackReason::none;
DmacManager::EnableCompletedInterrupt(DmacChanTmcRx);
- sercom->USART.CTRLB.reg |= (SERCOM_USART_CTRLB_RXEN | SERCOM_USART_CTRLB_TXEN); // enable transmitter and receiver
+ sercom->USART.CTRLB.reg |= (SERCOM_USART_CTRLB_RXEN/* | SERCOM_USART_CTRLB_TXEN*/); // enable transmitter and receiver
+ SetupDMARead(readRegNumber);
#else
uart->UART_IER = UART_IER_ENDRX; // enable end-of-receive interrupt
uart->UART_CR = UART_CR_RXEN | UART_CR_TXEN; // enable transmitter and rec